Advances in IC design and manufacturing are essential to the development of electronic devices that operate at faster speed and consume less power. Adding more functionality and interfaces to an IC while reducing the size of the IC remains a challenge. The increasing number of interfaces and functionality in designs today demands ever more pads for power supply and inputs/outputs (I/Os), which undesirably result in larger die sizes (e.g., pad-limited design).
The traditional wire bond technique has its limitation because only the periphery of the die is used for external connection pads thus limiting the number of pads that may be used. Furthermore, long bond wires have resistive, inductive, and capacitive components that affect the performance of the packaged IC. Additional routing layers have to be used to bring the external signals, and power and ground terminals to the interior circuitry of the IC. Such problems have been partly addressed by flip chip techniques. In a flip chip, the pads (interchangeably referred to as bumps or bump pads) are disposed over the surface of the chip instead of along its periphery. The number of pads is increased and the routing to the internal logic of the chip is shorter comparing with wire-bond techniques. Flip chip technology thus has high electrical performance due to the relatively low resistive, inductive and capacitive parasitics with a higher number of pads in a relatively small-sized package.
A Flip-chip package uses solder bumps deposited on the chip pads to establish connections to external circuits. The solder bumps are disposed on the top layer of the chip. The chip is mounted upside down with its top layer facing down so that the bump pads are aligned with the solder pads of an external circuit. FIG. 1 is a cross-sectional view of a flip-chip mounted with its top layer facing down to a package carrier. As shown, a flip-chip 100 includes multiple bump pads 102 on a redistribution layer 104 and multiple solder bumps 106 associated with the bump pads. Redistribution layer 104 may include multiple I/O drivers 110 and is disposed on a top metal layer 108. Flip-chip 100 may also include a semiconductor layer 116 disposed on a substrate 118. Flip-chip 100 may further include multiple metal layers including a first metal layer 114 disposed on semiconductor layer 116 and multiple dielectric layers (not shown) interposed between the metal layers. Semiconductor layer 116 includes electronic devices such as transistors, resistors, capacitors, inductors, memory elements that may be connected to each other and to the bump pads through the multiple metal layers. Flip-chip 100 is mounted upside down with solder bumps 106 connected to a package carrier 120.
FIG. 2 is a top view of an exemplary bump pad layout 210 and nets/wires 212 of a flip-chip 200. As shown, bump pad layout 210 includes multiple bump pads 220 (shown as octagon), multiple I/O drivers 230 (shown as the two internal rings), and multiple power/ground rings 240. Bump pads 220 may include core bump pads and I/O bump pads that are connected to other regions of flip-chip 200 using nets/wires 212 on a redistribution layer 206. Bump layout 210 may have core bump pads disposed at the central region and I/O bump pads at the peripheral region. Redistribution layer 206 may include one or more nets/wires 212 connected to I/O drivers 230 through I/O pads 232 and one or more nets 212 connected to power/ground rings 240 through power/ground pads 242. As a result of placing the core bump pads in the interior of the flip-chip and the I/O bump pads near the periphery, connections between the core bump pads and the I/O drivers and the power/ground rings can become challenging.
FIG. 3 is a straight-line routing of a portion 300 of a flip-chip, as known in the prior art. Portion 300 of a redistribution layer includes three rows of bump pads having a similar size. The bump pads are represented by octagons. As shown, spaces 303, 305 between bump pads in two adjacent rows 311, 313 are used for traces 321, 323, i.e., there is no space available for power routing from the core bump pads in the core region to the peripheral region. The problem is further exacerbated as the wire for power routing must have a large width to reduce the resistive, inductive and capacitive parasitics due to the long connection wiring from the core region to the peripheral region.